This invention relates to propagation delay control devices in logic circuitry and more specifically to methods and structures for maintaining constant time delays in semiconductor structure irrespective of processing factors and external environmental conditions such as temperature and power supply voltage.
Generally, it is expected that a given digital signal will appear at a given location within a circuit during a particular period of time. For example, when reading a memory device such as a ROM, it is expected that data information will be provided on the data output leads within a given period of time after the receipt of appropriate addressing and enabling signals. In other words, after the receipt of the desired address to be read, and a chip enable or output enable signal, the data signals are expected to appear not sooner than T1 seconds thereafter, and not later than T2 seconds thereafter. The reason for this is that the circuitry which is to receive the data information is constructed in a manner which requires the data information to be provided during this time period. If this data information is provided before time T1, previous data may be lost. If the data is not provided during the period between time T1 and time T2, the data will not be received. If the data is continued to be provided after time T2, additional data, such as is provided by another memory device or other circuitry may be lost.
In a similar manner, binary signals from any one of a number of circuits must appear at a selected node during a given period of time. Due to the variations in propagation delays caused by a number of factors, such as specific processing parameters, power supply voltage levels, ambient temperatures of the device, and the like, it is often times difficult or impossible to ensure that data is provided during the appropriate window of time. In many silicon semiconductor devices, the propagation delay of a gate can vary significantly depending on process variations, temperatures, and the like.